1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and a design method for designing circuit patterns to be produced in the semiconductor integrated circuit device.
2. Description of the Related Art
In manufacturing a semiconductor integrated circuit device, an interconnection layer defining various circuit patterns is formed in each of insulating layers, which are formed on a substrate of a semiconductor integrated circuit device, by using a photolithography and etching method.
In particular, in the photolithography and etching method, first, a suitable metal layer is formed on an insulating layer on the substrate of the semiconductor integrated circuit device, and a photoresist layer is formed on the metal layer. Then, a photomask defining various circuit patterns is applied to the photoresist layer, and then an exposure process is executed. Namely, in the exposure process, the photomask is exposed to a light through a suitable optical lens system, so that the various circuit patterns are optically projected and transferred from the photomask to the photoresist layer.
Next, the photoresist layer is developed by a developing process so that a photoresist pattern layer carrying the transferred circuit patterns is formed on the metal layer. Then, the metal layer is subjected to an etching process, and is patterned due to the existence of the photoresist pattern layer, so that an interconnection layer defining the various circuit patterns is produced on the insulating layer on the substrate of the semiconductor integrated circuit device.
On the other hand, an interconnection layer may be formed in the insulating layer on the substrate of the semiconductor integrated circuit device by using a damascene process.
Recently, with the advance of miniaturization of semiconductor integrated circuit devices, the minimum line width of the interconnection layer to be produced has become increasingly smaller. In reality, an interconnection layer featuring a minimum line width of less than 90 nm has been produced on the insulating layer formed on the substrate of a semiconductor integrated circuit device.
In general, in the exposure process of the photolithography and etching method, when a fine part of the circuit patterns to be optically projected and transferred from the photomask to the photoresist layer has a line width of less than ½ wavelength of light, it is difficult to carry out the optical transfer of the fine part from the photomask to the photoresist layer with proper fidelity, because an adequate depth of focus cannot be obtained at the fine part having the line width of less than ½ wavelength of light.
Various circuit patterns for a photomask are designed on a computer with a monitor.
When some patterns having a periodicity are defined in the photomask, an adequate depth of focus can be obtained at the periodic circuit patterns in an exposure process of a photolithography and etching method, so that an optical transfer of the periodic circuit patterns from the photomask to a photoresist layer can be carried out with proper fidelity.
On the other hand, when a circuit pattern is defined as a small and isolated circuit pattern such as a dot-pattern in the photomask, an adequate depth of focus cannot be obtained at the small and isolated circuit pattern in the exposure process, so that an optical transfer of the small and isolated circuit pattern from the photomask to the photoresist layer cannot be carried out with proper fidelity.
In order to improve the fidelity of the circuit patterns in the exposure process, Japanese Laid-Open Patent Publication (KOKAI) No. 2005-062601 discloses that an optical proximity correction (OPC) method is introduced into a design of circuit patterns. Namely, for example, in the OPC method, fine lines forming a circuit pattern are thickened, taking into account margins in relation to other parts of the circuit pattern.
On the other hand, recently, a grid-type design method has been proposed in order to effectively design a large-scale circuit pattern on a computer with a monitor, as will be explained in detail hereinafter.
In particular, in the grid-type design method, a grid is displayed on a monitor screen so that a plurality of minimum unit areas are defined by the grid. For example, each of the minimum unit areas may be defined as a square area having four sides of less than 100 nm.
A design of circuit patterns is carried out on the grid on the monitor screen by using a suitable drawing program installed in the computer. For example, in the design of circuit patterns, when a circuit pattern is defined and drawn as a line segment having some minimum unit areas continuously aligned with each other, the minimum unit areas forming the line segment are displayed on the monitor screen with a suitable single-color which is different from that of the background.
Also, in the design of circuit patterns, a circuit pattern may be defined and drawn as a previously-prepared basic pattern unit which is used to design a primitive section, i.e., a logic circuit section including basic function circuits, inverters, NAND circuits, NOR circuits, an analog core section, an input/output (I/O) section and so on.
After the design of circuit patterns is completed on the computer with the monitor, a photomask is produced based on the design of circuit patterns, and then is used in an exposure process of a photolithography and etching method to optically transfer the circuit patterns from the photomask to a photoresist layer, as stated hereinbefore.
It has now been discovered that the above-mentioned prior art grid-type design method has problems to be solved as mentioned below.
When any one of the circuit patterns is defined as a small and isolated circuit pattern, an adequate depth of focus cannot be obtained at the small and isolated circuit pattern in the exposure process of the photolithography and etching method, so that an optical transfer of the small and isolated circuit pattern from the photomask to the photoresist layer cannot be carried out with proper fidelity, resulting in decline of the manufacturing yield of semiconductor integrated circuit devices.